nixpkgs / arachne-pnr - Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys [0] synthesis suite for example. It currently targets the Lattice Semiconductor iCE40 family of FPGAs [1]. Its output is a textual bitstream representation for assembly by the IceStorm [2] icepack command.

Homepage - https://github.com/cseed/arachne-pnr

License - MIT

Maintainers - Shell Turner - Austin Seipp

Releases

2019.07.29 (expand/collapse)
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2018.09.09 (expand/collapse)
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2019.07.29 (expand/collapse)
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2019.07.29 (expand/collapse)
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2016.05.21 (expand/collapse)
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2017.12.06 (expand/collapse)
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